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Cypress Semiconductor /psoc63 /GPIO /PRT[6] /INTR_SET

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Interpret as INTR_SET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EDGE0)EDGE0 0 (EDGE1)EDGE1 0 (EDGE2)EDGE2 0 (EDGE3)EDGE3 0 (EDGE4)EDGE4 0 (EDGE5)EDGE5 0 (EDGE6)EDGE6 0 (EDGE7)EDGE7 0 (FLT_EDGE)FLT_EDGE

Description

Port interrupt set register

Fields

EDGE0

Sets edge detect interrupt for IO pin 0 ‘0’: Interrupt state not affected ‘1’: Interrupt set
EDGE1

Sets edge detect interrupt for IO pin 1
EDGE2

Sets edge detect interrupt for IO pin 2
EDGE3

Sets edge detect interrupt for IO pin 3
EDGE4

Sets edge detect interrupt for IO pin 4
EDGE5

Sets edge detect interrupt for IO pin 5
EDGE6

Sets edge detect interrupt for IO pin 6
EDGE7

Sets edge detect interrupt for IO pin 7
FLT_EDGE

Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data